1. Field of the Invention
This invention relates to designing integrated circuits, and more particularly to a methodology for designing application specific integrated circuits (ASICs) that places buffers between modules of an ASIC so that design changes to an upstream module do not readily propagate to downstream modules and cause design changes to the downstream modules.
2. Related Art
Circuit design is presently accomplished primarily through the use of computer aided design (CAD) tools, which take as input a circuit specification and automatically generate and simulate circuit descriptions suitable for implementation. One type of circuit commonly designed using CAD tools is an application specific integrated circuit (ASIC). ASICs are often very complex. Consequently, design of an AGIC is typically accomplished by dividing an ASIC into a plurality of modules, which are designed separately-often by different designers. This process of dividing an ASIC into modules has a number of advantages. It is more efficient computationally to synthesize and test modules of a circuit independently first, so that module designs are stabilized before synthesizing and testing a complete circuit. Furthermore, breaking up a circuit into separately designed modules allows a circuit to be designed by a group of designers working somewhat independently on separate modules.
However, this process of dividing a circuit gives rise to a number of problems in ultimately recombining the modules into a circuit. For example, a change to an input signal of a module may cause changes to characteristics of an output signal from the module. This may cause the input to a downstream module to change, which may cause an output of the downstream module to change, and so on, until the changes propagate through many modules in the circuit. Each time an output changes, the circuit may have to be re-synthesized and/or re-tested, which can be a very time-consuming process. Consequently, this potential rippling of changes through a circuit can greatly increase the time required to design a circuit, and may ultimately lead to increased costs for the circuit.
Furthermore, if an output signal from a module may be affected feeds back into the module, the signal that feeds back into the module may be affected by downstream loads on the output signal. Consequently, downstream connections of the output signal may affect the timing of signals within the module, which may trigger changes in the design of the module.
Additionally, when modules are integrated together, signals are often not routed optimally because output drivers are placed at various locations during the design of a module without regard for the effect of such placement on the optimal routing of signals between modules.
What is needed is a method for designing a circuit that limits the ability of design tools to automatically change the characteristics of signals travelling between modules, so that design changes to a module do not needlessly create design changes in downstream modules of a circuit.
Additionally, what is needed is a method for designing a circuit that insulates output signals that feed back into a module from the effects of loads placed on the output signals outside the module.
Furthermore, what is needed is a method for designing a circuit that carefully locates output drivers for modules of the circuit, so that signals are more optimally routed between modules of a circuit.